Paper Title
Set-Level Capacity-Sharing and Energy-Efficient Cache Coherence Protocol in Multicore Processors

Abstract
Multicore processors have been widely used to improve system performance. However, when a miss occurs in a private cache, actions including maintaining data coherence between the private caches and accessing the desired data from the shared cache increase energy consumption and reduce system performance. In this paper, in order to improve system performance and reduce energy consumption, we take into account spatial and temporal locality to reduce the access times for the shared cache. Considering spatial locality, we propose a dynamic set-level capacity-sharing mechanism (DSCSM) to share a set having a lower utility rate with that having a higher utility rate to reduce the access times for the shared cache. In addition, to make the proposed DSCSM work and thereby reduce energy consumption, we propose an energy-aware cache coherence protocol to reduce the times of comparing tags. Finally, a dynamic replacement strategy (DRS) that detects the characteristics of an executing application dynamically to apply an appropriate replacement strategy is proposed, which takes into account temporal locality. The simulation results showed that the proposed DSCSM and DRS consumed less energy than the traditional two-level cache with the MESI protocol and cooperative caching (CC) by 46% and 31%, respectively. Moreover, the proposed design exhibited a shorter execution time than the traditional two-level cache with the MESI protocol and CC by about 10% and 3%, respectively. Keywords - Multicore Processor, Private Cache, Cache Locality, Capacity Sharing, Cache Coherence

Author - You-Wei Zhan, Chi-Chao Hung, Han-Chun Chen, Ching-Wen Chen

Published : Volume-6,Issue-9  ( Sep, 2019 )

	|		PDF	|	Viewed - 44	|	Published on 2019-11-28