Paper Title
A Survey on Hardware and Software Co-Simulation Environment

Abstract
Electronic systems are becoming more complex rapidly. System Validation and verification of these increasing software complexities requires some new ways. Verifying hardware and software design together increases debugging capabilities faster and easier at early stages of design. Since, hardware and software is used with different simulators. The important objective is to build environment including both hardware and software simulators with an interactive channel between them. This paper surveys the need for co-simulation environment and techniques for accelerating the co-simulation. Keywords - Hardware And Software Co-Simulation, PLI, Verilog, Simulation, Verification, Socket, Models.