Paper Title
High Speed Single Precision Floating Point Unit Implementation Using Verilog
Abstract
Abstract: To represent very large or small values, large range is required as the integer representation is no longer
appropriate. These values can be represented using the IEEE-754 standard based floating point representation. This paper
presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition, subtraction,
multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. Pre-normalization unit and post
normalization units are also discussed along with exceptional handling. All the functions are built by feasible efficient
algorithms with several changes incorporated that can improve overall latency, and if pipelined then higher throughput. The
algorithms are modeled in Verilog HDL and the RTL code for adder, subtractor, multiplier, divider, square root are
synthesized using Cadence RTL complier where the design is targeted for 180nm TSMC technology with proper constraints.
Keywords: floating point number, normalization, exceptions, latency, overflow, underflow, etc