Paper Title
FPGA Implementation Of Multiplier Using Shift And Add Technique

Multipliers are one of the most important parts in signal processing or other computationally intensive applications. Therefore, designing multipliers that are high speed, low power and less area of substantial research interest. Many attempts have been made to reduce the number of partial products generated by multiplication process. The aim of this paper is to Implement a Multiplier block using shift and Add technique of multiplication in an FPGA. The implementation is done by using Xilinx 14.5 version of VHDL with the targeted device of Spartan 3E. The performance of Multiplier unit is evaluated for various parallel prefix adder variants, which are developed for high speed addition. The experimental results shows that the implemented Multiplier using hybrid parallel prefix adder is efficient in area, consume low power and high speed compared to existing parallel prefix adder models. Keywords - Multiplier, Shift and Add, Field Programmable Gate Array (FPGA), Digital Signal Processing (DSP), Parallel Prefix Adder (PPA).