Paper Title
A Review on Verification of APIs using SystemVerilog and UVM

With the rapid development of SoCs, manufacturing technologies and computer aided design (CAD) tools, design of SoCs is becoming complex than before. As the design becomes complex, verification time grows exponentially. Therefore, it is required to reduce the verification time under time to market pressure. Universal Verification Methodology (UVM) makes this possible by providing a library of base classes which can be used for the required functionality. In this paper, a review of verification of APIs using SystemVerilog and UVM is presented. Keywords - SystemVerilog, UVM, Coverage, APIs.