A Robust Frequency Compensation Technique for on-Chip Output Capacitor Three Stage Low-Drop-Out Linear Regulator
A novel compensation technique is proposed to improve the stability and transient response of the on-chip output capacitor three stage low-drop-out linear regulator (LDO). It exploits the current buffer and current amplifier circuits to multiply the classical Miller compensation effect by increasing the loop gain of the compensation bloc in order to guarantee the stability of the LDO regulator for all required range of the load current and especially for ultra light load current and also enhance the transient response in terms of speed. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18um low voltage CMOS process. The presented LDO regulator delivers a stable voltage of 1.2V for an input supply voltage range of 1.35-1.85V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is less than 65mV when the load current pulses from 150mA to 0mA during a fall time of 1us. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.
Keywords - LDO Regulator, Zero Load Current Stability, Current Buffer, Current Amplifier, Transient Load Regulation.