Paper Title
A Novel Approach Of Low Power Area And Delay Efficient Ladder Fischer Carry Select Adder

An capable CSLA model is obtained using modifications in the logic units. In the proposed design ripple carry adder the circuit is being replaced with ladner-fischer based adder(lf). We have eliminate all the redundant logic operations in attendance in the conventional CSLA and proposed a new logic formulation for new CSLA. In the proposed method the carry select (CS) operation is planned previous to the calculation of final-sum, which is extraordinary from the conventional approach. Bit patterns of two expect carry words (corresponding to cin =0and 1) and fixed c bits are used for logic optimization of CS and construction units. The high pace of operation and not as much of area overhead in case of ladner- fischer based adder compare to ripple carry adder. The proposed CSLA design involve significantly less area and delay than the newly proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good nominee for square-root (SQRT) CSLA. Prefix adders are tree structure based and are preferred to speed up the binary additions. Carry Select Adder (CSLA) is one of the best ever adders used in many data-processing processors to perform fast arithmetic functions. From the configuration of the CSLA, it is understandable that there is possibility for reducing the area and power expenditure in the CSLA. This work uses a straightforward and efficient modification to significantly reduce the area and power of the CSLA. Based on this modification 16b square-root CSLA (SQRT CSLA) construction have been developed and compared with the regular SQRT CSLA structural design. The proposed design has reduced area and power as compared with the regular SQRT CSLA. This work evaluate the performance of the proposed designs in terms of delay, area, power, and memory The outcome analysis shows that the proposed CSLA structure is superior than the regular SQRT CSLA. Keywords- CSLA, Area delay performance, conventional carry select adder, arithmetic unit, low-power design.