Paper Title
Novel Design Of Dual Core RISC Architecture Implementation

The main goal of the project is simulation and synthesis of the 17bit RISC CPU based on MIPS.RISC is a style or family of processor architecture that share some characteristics and that has been designed to perform a small set of instructions. The most important feature of the RISC processor is that this processor is very simple and support load and store architecture. The design uses Harvard architecture which has distinct program memory space and data memory space. The design consists of four stage pipelining, which involves instruction fetch, instruction decode, execute and write back stage. In this project simulation is done by modelsim to perform logical verification and further synthesizing it on Xilinx-ISE tool using target technology and performing place & routing operation for system verification. The language used here is verilog. Keywords: MIPS, RISC, Pipelining, Xilinx.