Low Power Approach For Implementation Of Huffman Coding For High Data Compression
In this paper a clock gated Huffman encoder and decoder circuit implementation is presented. The Huffman
circuit is designed with gated clock as it optimized the power dissipation without degrading the performance. This paper
aims to implementing, analyzing and comparing the various resource power using clock gating techniques to Huffman
design on a 130 nm library. The technology used in this paper is gated clock circuit using different types of clock gating to
get the best performance for Huffman design. Gated clock is used to control the encoder and decoder circuit. The results of
design shows that using AND based clock gating technique is better than latch based clock gating. It reduces power and area
more than latch based clock gating. The proposed Huffman design is implemented by using ASIC design methodologies
with 130 nm technology library. The architecture of Huffman design has been created using Verilog HDL language, Quartus
II 11.1 Web Edition (32-Bit). The simulation is carried out by using ModelSim-Altera10.0c (QuartusII 11.1) Starter Edition.
Keywords- Clock gating, Power Dissipation, Dynamic power, Low Power Techniques.