Design of MTCMOS Domino Logic For Ultra Low Power High Performance 3×3 Array Multiplier
Power consumption plays an imperative role specifically in the field of VLSI today. Thus, as the requirement of
low power high performance arithmetic circuits, in this paper a design of new MT-CMOS domino logic is introduced to
design an array multiplier circuit. The MT-MOS transistors reduce the power dissipation by minimizing sub threshold
leakage current in domino logic circuits introduced. The MT-NMOS transistor connected in discharging path of output
inverter can be applied for pipeline structure to reduce the power consumptions and increase fan-out. Dynamic logic style
CMOS circuit is used to improve the speed and reduce the area of design by decreasing the device count. The combination of
MT-CMOS and dynamic logic circuit provides high fan-out, high switching frequencies since both lower delay and dynamic
power consumption. The simulation results of these proposed low power high performance circuits are provides average
power reduction and active area minimization.
Index terms- MT-CMOS, Domino, Array Multiplier, subthreshold, Low power.